Therefore, in this work, to reduce the P/E voltage, we try to use p-channel devices with band-to-band tunneling-induced hot click here electron (BBHE) operation compared with Fowler-Nordheim (FN) operation and use a Ω-gate structure to have little deterioration. These p-channel twin fin field-effect transistor (FinFET) EEPROM devices with a Ω-gate structure have excellent retention and endurance. Methods First, a p-type undoped channel twin poly-Si TFT EEPROM with ten NWs was fabricated. Figure 1a presents the structure of the NW twin poly-Si TFT EEPROM. The gate electrodes

of two TFTs are connected to form the floating gate, while the source and drain of the larger TFT (T2) are connected to form the control gate. Figure 1b presents the transmission electron microscopy (TEM) image of the NW EEPROM perpendicular

to CYT387 solubility dmso the gate direction; the NWs are surrounded by the gate electrode as a Ω-gate structure with an effective width of 113 nm. Figure 1 Schematic, TEM image, and equivalent circuit of twin poly-Si TFT EEPROM. (a) Schematic of the twin poly-Si TFT EEPROM cell with ten NWs. (b) The TEM image of Ω-gate NW twin poly-Si TFT EEPROM. The effective channel width is 113 nm × 10 [(61 nm + 16 nm × 2 + 10 nm × 2) × 10)]. (c) The equivalent circuit of twin poly-Si selleck inhibitor TFT EEPROM. These devices were fabricated by initially growing a 400-nm-thick thermal oxide layer on 6-in. silicon wafers as substrates. A thin 50-nm-thick undoped amorphous Si (a-Si) layer was deposited by low-pressure chemical vapor deposition (LPCVD) at 550°C. The deposited a-Si layer was then solid-phase-crystallized at 600°C for 24 h in nitrogen ambient. The device’s active NWs were patterned by electron beam (e-beam) direct writing and transferred by reactive-ion etching (RIE). Then, they were dipped into HF solution for 60 s to form the Ω-shaped structure. For gate dielectric, a 15-nm-thick layer of thermal oxide was grown as tunneling oxide. Then, a 150-nm-thick Erastin nmr poly-Si layer was deposited and transferred to a floating gate by electron beam direct writing and

RIE. Then, the T1 and T2 self-aligned P+ source/drain and gate regions were formed by the implantation of BF2 ions at a dose of 5 × 1015 cm−2. The dopant was activated by ultrarapid thermal annealing at 1,000°C for 1 s in nitrogen ambient. Then, a 200-nm-thick TEOS oxide layer was deposited as the passivation layer by LPCVD. Next, the contact holes were defined and 300-nm-thick AlSiCu metallization was performed. Finally, the devices were then sintered at 400°C in nitrogen ambient for 30 min. In programming, the electrons tunnel into T1 through the tunneling oxide. The tunneling oxide of NW-based EEPROM is surrounded by the gate electrode (Figure 1b). Figure 1c shows the equivalent circuit of this twin TFT NVM: (1) To maximize the voltage drop in the tunnel oxide of T1, the gate capacitance of T2 (C2) must exceed the gate capacitance of T1 (C1).