Nanoscale

Nanoscale Torin 2 price Res Lett 2011, 6:41. 7. Ichikawa K, Uraoka Y, Yano H, Hatayama T, Fuyuki Y, Takahashi E, Hayashi T, Ogata K: Low temperature polycrystalline silicon thin film transistors flash memory with silicon nanocrystal dot. Jpn J Appl Phys 2007, 46:661.CrossRef 8. Lai EK, Lue HT, Hsiao YH, Hsieh JY, Lu CP, Wang SY, Yang LW, Yang T, Chen KC, Gong J, Hsieh KY, Liu R, Lu CY: A highly stackable thin-film transistor (TFT) NAND-type flash memory. VLSI Tech Dig 2006, 2006:46. 9. Chung HJ, Lee NI, Han CH: A high-endurance low-temperature polysilicon thin-film transistor EEPROM cell. IEEE Pifithrin-�� nmr Electron Device Lett 2000, 21:304.CrossRef 10. Wu TC, Chang TC, Chang CY, Chen CS, Tu CH, Liu PT,

Zan HW, Tai YH: High-performance polycrystalline silicon thin-film transistor with multiple nanowire channels and lightly doped drain structure. Appl Phys Lett 2004, 84:19.CrossRef 11. Gabrielyan N, Saranti K, Manjunatha KN, Paul S: Growth of low temperature silicon nano-structures Eltanexor price for electronic and

electrical energy generation applications. Nanoscale Res Lett 2013, 8:83.CrossRef 12. Lacy F: Developing a theoretical relationship between electrical resistivity, temperature, and film thickness for conductors. Nanoscale Res Lett 2011, 6:636.CrossRef 13. Wu YC, Su PW, Chang CW, Hung MF: Novel twin poly-Si thin-film transistors EEPROM with trigate nanowire structure. IEEE Electron Device Lett 2008, 29:1226.CrossRef 14. Wu YC, Hung MF, Su PW: Improving the performance of nanowires polycrystalline silicon twin thin-film transistors nonvolatile memory by NH 3 plasma passivation. J Electrochem Soc 2011, 158:H578.CrossRef Competing interests The authors declare that they have no competing interests. Ergoloid Authors’ contributions M-SY and M-FH carried out the device mask layout, modulated the coupling ratio of the device, handled the experiment, and drafted the manuscript. K-CL measured the characteristics of the device and made the simulation plot. Y-RJ and L-CC gave some physical explanation to this work. Y-CW conceived the idea of low-temperature deposition of twin FinFET and their exploitation into devices.

He also supervised the work and reviewed the manuscript. C-YC participated in the design and coordination of the study. All authors read and approved the final manuscript.”
“Introduction Since 2004, the monolayer graphene has been successfully realized in experiment [1, 2]. Subsequently, its intriguing properties originating from the strictly two-dimensional structure and massless Dirac fermion-like behavior of low-energy excitation have attracted intensive attention [3, 4]. Graphene can be tailored into various edge nanoribbons. Their semiconducting properties with a tunable band gap dependent on the structural size and geometry make them good candidates for the electric and spintronic devices [5]. Due to this reason, the graphene nanoribbons (GNRs) become of particular interest.

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